/**********************************************************************************************************************
 *  COPYRIGHT
 *  -------------------------------------------------------------------------------------------------------------------
 *
 *                This software is copyright protected and proprietary to Vector Informatik GmbH.
 *                Vector Informatik GmbH grants to you only those rights as set out in the license conditions.
 *                All other rights remain with Vector Informatik GmbH.
 *  -------------------------------------------------------------------------------------------------------------------
 *  FILE DESCRIPTION
 *  -------------------------------------------------------------------------------------------------------------------
 *          File:  Rte_AppCtrl.h
 *        Config:  GL_Demo2.dpa
 *   ECU-Project:  XB_SUP_F
 *
 *     Generator:  MICROSAR RTE Generator Version 4.19.0
 *                 RTE Core Version 1.19.0
 *       License:  CBD1800257
 *
 *   Description:  Application header file for SW-C <AppCtrl>
 *********************************************************************************************************************/

/* double include prevention */
#ifndef _RTE_APPCTRL_H
# define _RTE_APPCTRL_H

# ifndef RTE_CORE
#  ifdef RTE_APPLICATION_HEADER_FILE
#   error Multiple application header files included.
#  endif
#  define RTE_APPLICATION_HEADER_FILE
#  ifndef RTE_PTR2ARRAYBASETYPE_PASSING
#   define RTE_PTR2ARRAYBASETYPE_PASSING
#  endif
# endif

# ifdef __cplusplus
extern "C"
{
# endif /* __cplusplus */

/* include files */

# include "Rte_AppCtrl_Type.h"
# include "Rte_DataHandleType.h"


# define RTE_START_SEC_CODE
# include "MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */

/**********************************************************************************************************************
 * API prototypes
 *********************************************************************************************************************/
FUNC(Std_ReturnType, RTE_CODE) Rte_Read_AppCtrl_SG_Sig_Grp_0x300_SR_R_SG_Sig_Grp_0x300(P2VAR(SG_Sig_Grp_0x300, AUTOMATIC, RTE_APPCTRL_APPL_VAR) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Read_AppCtrl_SG_Sig_Grp_0x301_SR_R_SG_Sig_Grp_0x301(P2VAR(SG_Sig_Grp_0x301, AUTOMATIC, RTE_APPCTRL_APPL_VAR) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Read_AppCtrl_SG_Sig_Grp_0x302_SR_R_SG_Sig_Grp_0x302(P2VAR(SG_Sig_Grp_0x302, AUTOMATIC, RTE_APPCTRL_APPL_VAR) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Read_AppCtrl_SG_Sig_Grp_0x304_SR_R_SG_Sig_Grp_0x304(P2VAR(SG_Sig_Grp_0x304, AUTOMATIC, RTE_APPCTRL_APPL_VAR) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x210_SR_S_SG_Sig_Grp_0x210(P2CONST(SG_Sig_Grp_0x210, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x211_SR_S_SG_Sig_Grp_0x211(P2CONST(SG_Sig_Grp_0x211, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x212_SR_S_SG_Sig_Grp_0x212(P2CONST(SG_Sig_Grp_0x212, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x213_SR_S_SG_Sig_Grp_0x213(P2CONST(SG_Sig_Grp_0x213, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x214_SR_S_SG_Sig_Grp_0x214(P2CONST(SG_Sig_Grp_0x214, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */
FUNC(Std_ReturnType, RTE_CODE) Rte_Write_AppCtrl_SG_Sig_Grp_0x216_SR_S_SG_Sig_Grp_0x216(P2CONST(SG_Sig_Grp_0x216, AUTOMATIC, RTE_APPCTRL_APPL_DATA) data); /* PRQA S 0850 */ /* MD_MSR_19.8 */

# define RTE_STOP_SEC_CODE
# include "MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */


# ifndef RTE_CORE

/**********************************************************************************************************************
 * Rte_Read_<p>_<d> (explicit S/R communication with isQueued = false)
 *********************************************************************************************************************/
#  define Rte_Read_SG_Sig_Grp_0x300_SR_R_SG_Sig_Grp_0x300 Rte_Read_AppCtrl_SG_Sig_Grp_0x300_SR_R_SG_Sig_Grp_0x300
#  define Rte_Read_SG_Sig_Grp_0x301_SR_R_SG_Sig_Grp_0x301 Rte_Read_AppCtrl_SG_Sig_Grp_0x301_SR_R_SG_Sig_Grp_0x301
#  define Rte_Read_SG_Sig_Grp_0x302_SR_R_SG_Sig_Grp_0x302 Rte_Read_AppCtrl_SG_Sig_Grp_0x302_SR_R_SG_Sig_Grp_0x302
#  define Rte_Read_SG_Sig_Grp_0x304_SR_R_SG_Sig_Grp_0x304 Rte_Read_AppCtrl_SG_Sig_Grp_0x304_SR_R_SG_Sig_Grp_0x304


/**********************************************************************************************************************
 * Rte_Write_<p>_<d> (explicit S/R communication with isQueued = false)
 *********************************************************************************************************************/
#  define Rte_Write_SG_Sig_Grp_0x210_SR_S_SG_Sig_Grp_0x210 Rte_Write_AppCtrl_SG_Sig_Grp_0x210_SR_S_SG_Sig_Grp_0x210
#  define Rte_Write_SG_Sig_Grp_0x211_SR_S_SG_Sig_Grp_0x211 Rte_Write_AppCtrl_SG_Sig_Grp_0x211_SR_S_SG_Sig_Grp_0x211
#  define Rte_Write_SG_Sig_Grp_0x212_SR_S_SG_Sig_Grp_0x212 Rte_Write_AppCtrl_SG_Sig_Grp_0x212_SR_S_SG_Sig_Grp_0x212
#  define Rte_Write_SG_Sig_Grp_0x213_SR_S_SG_Sig_Grp_0x213 Rte_Write_AppCtrl_SG_Sig_Grp_0x213_SR_S_SG_Sig_Grp_0x213
#  define Rte_Write_SG_Sig_Grp_0x214_SR_S_SG_Sig_Grp_0x214 Rte_Write_AppCtrl_SG_Sig_Grp_0x214_SR_S_SG_Sig_Grp_0x214
#  define Rte_Write_SG_Sig_Grp_0x216_SR_S_SG_Sig_Grp_0x216 Rte_Write_AppCtrl_SG_Sig_Grp_0x216_SR_S_SG_Sig_Grp_0x216


# endif /* !defined(RTE_CORE) */


# define AppCtrl_START_SEC_CODE
# include "AppCtrl_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */

/**********************************************************************************************************************
 * Runnable entities
 *********************************************************************************************************************/

# ifndef RTE_CORE
#  define RTE_RUNNABLE_AppCtrl_Init AppCtrl_Init
#  define RTE_RUNNABLE_AppCtrl_MainFunction AppCtrl_MainFunction
# endif

FUNC(void, AppCtrl_CODE) AppCtrl_Init(void); /* PRQA S 0850, 3451 */ /* MD_MSR_19.8, MD_Rte_3451 */
FUNC(void, AppCtrl_CODE) AppCtrl_MainFunction(void); /* PRQA S 0850, 3451 */ /* MD_MSR_19.8, MD_Rte_3451 */

# define AppCtrl_STOP_SEC_CODE
# include "AppCtrl_MemMap.h" /* PRQA S 5087 */ /* MD_MSR_19.1 */

# ifdef __cplusplus
} /* extern "C" */
# endif /* __cplusplus */

#endif /* _RTE_APPCTRL_H */

/**********************************************************************************************************************
 MISRA 2004 violations and justifications
 *********************************************************************************************************************/

/* module specific MISRA deviations:
   MD_Rte_3451:  MISRA rule: 8.8
     Reason:     Schedulable entities are declared by the RTE and also by the BSW modules.
     Risk:       No functional risk.
     Prevention: Not required.

*/
